1. Field of the Invention
The present invention generally relates to a method for forming interconnect structures, particularly to a method for forming interconnect structures having airgaps.
2. Description of the Related Art
As the dimension between metal lines decreases for each successive technology node, it is necessary to continue scaling down the capacitance between metal lines to reduce cross-talk and RC delay. Towards this objective, the k value (dielectric constant) of dielectric materials has been scaled down aggressively in the past decade from 4.0 to about 2.5. Leading edge manufacturing companies have recently reached a Keff of about 2.7 (effective k value) with the use of low-k CDO (carbon doped oxide) having a k value of about 2.5 and SiCN dielectric diffusion barrier having a k value of about 5.0. In order to achieve scaling Keff significantly below 2.5, a further decrease of k value from 2.5 to less than 2.3 will be required. The ITRS roadmap stated the target k value for bulk dielectric should be about 2.2 for a 22-nm technology node. However, it has been difficult to develop a dielectric material having a k value of less than 2.5 with good mechanical and suitable integration properties. For example, if a high porosity material is used for forming a dielectric film having a k value of less than 2.5, its mechanical strength will be significantly degraded. In addition, high porosity can lead to connected-pore problems, causing severe process integration challenges (e.g., diffusion problems in ALD/CVD-based metal process technology).
Considering the above, drastic changes have been proposed to develop airgap technology to achieve a Keff reduction for future extendibility. Nevertheless, all of the airgap processes require drastic changes to the existing process schemes. For example, Hsien-Wei Chen, et al. (“A Self-aligned Airgap Interconnect Scheme,” Interconnect Technology Conference, 2009. IITC 2009. IEEE International, 1-3 Jun. 2009, pp. 146-148) use a plasma damage layer as a sacrificing layer for forming an airgap. Although this scheme does not require an additional patterning step for forming an airgap, it is difficult to control the thickness of airgap because the thickness of the plasma damage layer is not readily controllable. Patterning the airgaps is also difficult because it is difficult to deposit a sacrificing layer on sidewalls of trenches with high conformality. The conformality of a layer formed by thermal CVD tends to be better than that of plasma enhanced CVD, but thermal CVD requires high heat which is not suitable for metal (e.g., copper) interconnect structures.